Upcoming iPhones are going to rock. Here's why

TSMC has some amazing new processors in the works that will power future iPhone models.

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The TSMC log0o in front of a building in Taiwan.
As expected, TSMC has started volume production of chips using its N2 2nm process. This isn't really a surprise since the world's largest contract foundry previously said that it would be manufacturing such chips by Q4 this year. A small box on TSMC's website quietly mentions the start of 2nm production. It says, "TSMC's 2nm (N2) technology has started volume production in 4Q25 as planned. N2 technology features first-generation nanosheet transistor technology, with full-node strides in performance."

The reference to the "first-generation nanosheet transistor technology" is describing the new Gate-All-Around (GAA) transistor that is replacing the FinFET transistor. GAA transistors use the gate to cover the channel on all four sides with vertically placed nanosheets. This reduces current leaks and improves the drive current. As a result, chips made with GAA transistors usually feature an increase in performance and energy efficiency.

TSMC will introduce its Gate-All-Around transistors when it starts shipping its N2 production next year


TSMC's 2nm process will be the most advanced technology in the industry when it comes to transistor density and energy efficiency. Transistor density is the important number that will show you how advanced a chip is. The metric is usually expressed as the number of millions of transistors per square millimeter. This is where the process node comes into play. The lower the process node, the smaller are a chip's features including transistors. When you drop from, say the 3nm process node to 2nm, the transistors are smaller meaning that more can fit into a square millimeter increasing the performance and energy efficiency of a chip.

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Comparing the first generation of TSMC's 2nm process node (N2) with TSMC's third generation 3nm (N3E), the newer 2nm chip is 10% to 15% faster at the same power, uses 25% to 30% less energy at the same speed, and features a 15% increase in transistor density for mixed design chips that include logic, analog, and SRAM. For logic chips only, the transistor density for N2 will be 20% higher than the figure for N3E.

Is TSMC well positioned for the future?


A chip with a higher transistor density is more powerful. Consider that the 7nm A13 Bionic application processor (AP) that powered the iPhone 11 had a transistor density of 90–95 million transistors per square millimeter. For the 3nm A17 Pro AP that powered the iPhone 15 Pro and iPhone 15 Pro Max, transistor density was 220-290 million transistors per square millimeter. 

After 2nm TSMC will introduce the A16 (16 Angstrom)


And next year's iPhone 18 Pro Max will probably be powered by the 2nm A20 Pro AP which could have a transistor density of 310-330 million transistors per square millimeter. So, the transistor density on the AP used to power the iPhone has soared from 90-95 million for the A13 Bionic to an expected 310-330 million for next year's A20 Pro. 

The next question you might have is what happens after 2nm? TSMC will use its A16 (16 Angstrom) process which will include the Super Power Rail (SPR). Instead of cramming all of the connections and wires on the front of a silicon wafer, the power connections are made on the backside of the wafer. TSMC’s Super Power Rail connects the power source directly to the transistor’s source and drain allowing transistors to be packed more closely together allowing them to run more efficiently. Volume production of TSMC's A16 could start as soon as the second half of next year.

Also expected to start volume production in the second half of next year is the performance enhanced version of N2 known as N2P. The latter will deliver a 5% to 10% improvement in performance at the same power as the N2. At this stage, it's unclear what and if the improvement in transistor density will be going from N2 to N2P.

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