There's no doubt Samsung came up with a pretty fine chip developing the so-called octo-core Exynos 5 Octa mobile processor
. It was announced at the CES expo back in January, at a presentation, which, while not an off-Broadway show like the S4 unveiling
, was pretty high up their in visuals and celebs, and where even former President Bill Clinton took the stage
to endorse Samsung's efforts in making the world a better place, one gadget at a time.
At first we thought it might be because of LTE compatibility. Qualcomm's processor are a veritable system-on-a-chip (SoC) endeavor, as they have the broadband radios built into the chipset, instead of tacked on later, like with the Exynos series. It is not easy to develop a compact and frugal LTE chip with all the filters to avoid band interference, and make it play well with the other elements of a mobile processor without affecting battery life more than needed. Qualcomm has mastered this process, making it a breeze for manufacturers to just leave the Texans take care of everything related to processing and connectivity, and focus on design and added features.
What's the holdup? Well, it turns out that Samsung went with the simpler and cheaper way to design 28nm chips like the Exynos 5 Octa, called gate-first, while the competing foundry TSMC
designed its production capacity with the harder to implement gate-last process, developed by Intel. The problem stems from the fact that gate-first might be easier to transition to, but gives yield problems later on
, especially with complex SoCs, and that's exactly what seems to be happening with Exynos 5 Octa.
Here's the more scientific citation, eventually explained by one of Samsung's chip customers in the Silicon Valley:
Gate-first HKMG is easier to implement as a transition from a traditional poly/SION structure. The construction of the gate and transistor remain the same, though the materials are different (i.e., a high-k gate oxide instead of oxynitride); a metal gate is inserted, and then poly on top of that—and the rest of the flow is "basically the same as previous generation structures."
Gate-first also is "much simpler" to implement from a process migration standpoint in terms of IP implementation, and fewer restrictive design rules (gate-last requires CMP around the gate structure). "We can maintain 50% shrink from 45nm to 32nm because there's not as many restrictive design rules," Ana Hunter (VP foundry at Samsung Semiconductors) said. This makes the process particularly good for mobile applications, as it's cost-effective and "very good on gate leakage—a >100× improvement from 45nm to 32nm."