2020 Apple iPhones could be first to use a more powerful chip architecture

2020 Apple iPhones could be first to use a more powerful chip architecture
The smaller the process used to fabricate chips, the more transistors fit inside the densely packed space inside. That means higher performance and better energy consumption. For example, the original iPhone used an SoC that was manufactured using the 45nm process. Today's top chipsets, including the Snapdragon 855, are produced using the 7nm process. And with the use of extreme ultraviolet lithography (EUV), chip makers can more precisely design the layouts of integrated circuits (IC) for even more performance enhancements.

TSMC, the company that manufacturers many of the chips found in today's smartphones, plans on starting volume production of 5nm chips during the first quarter of next year. Preliminary figures show that these will be packed with 1.8 times the number of transistors found in the 7nm components with a 15% speed boost possible. Recent reports suggest that Samsung will manufacture the Qualcomm Snapdragon 865 instead of TSMC, and will do so using Sammy's 7nm EUV process. As a result, the 2020 iPhones might be the first smartphones to use a 5nm SoC.

Moore's Law, which was an observation made by Intel founder Gordon Moore states the number of transistors inside an IC double every other year. While this hasn't been followed perfectly, the number of transistors inside these components keeps rising.  TechWeb reports (via WCCF Tech) that TSMC is awaiting certain environmental approvals for the factories that will build 3nm chips in Hsinchu, Taiwan starting in 2022. TSMC senior director Zhuang Zishou says that it will conduct R&D for 2nm chips in the same city to avoid "brain drain."

As fast as 7nm chips are now, it is hard to imagine the blinding speed that will be available when chips made using the 2nm process become commonplace.

FEATURED VIDEO

15 Comments

1. pogba

Posts: 110; Member since: Jun 13, 2018

So where do we go after 1 nm?

3. cncrim

Posts: 1588; Member since: Aug 15, 2011

Amazing 0 lol

15. sgodsell

Posts: 7363; Member since: Mar 16, 2013

It's going to be really difficult, because the width of the smallest atom (hygrogen) is 0.1 nm. Plus gates have to because certain size. What OEMs can do is included RAM on the SoC as well, and I don't mean cache. I mean full fledged RAM. For instance put 8GB of RAM on the SoC. Then go from there to add more in the future. Plus they could add more cores.

4. Phullofphil

Posts: 1785; Member since: Feb 10, 2009

You Go down to the next unit of measure below nano witch you can look up any search engine. It just like meters centimeters millimeters it’s the on it’s just like meters, centimeters, millimeters and so on like angstrom

6. stferrari

Posts: 56; Member since: Dec 15, 2014

Picometer

2. Rocket

Posts: 653; Member since: Feb 24, 2014

-1 nm ;)

5. ph00ny

Posts: 2031; Member since: May 26, 2011

nm isn't the only defining factor for architectural advancement

7. domfonusr

Posts: 1084; Member since: Jan 17, 2014

Eventually, the IC makers will get to a point of diminishing returns when it comes to transistor size. Smaller and smaller transistors will become subject to ever-increasing quantum noise as size is reduced. The smaller the transistors get, the barrier potentials that separate the channels (potential wells in the transistor) in smaller transistors eventually present a small enough profile that electrons can cross them without activation - basically quantum barrier tunneling - which has the effect of introducing a gradually increasing background noise in the circuit as size decreases. This effect was once predicted to become significant at or below the 1 to 2nm mark.

8. Vokilam

Posts: 1191; Member since: Mar 15, 2018

Yeah but that’s why they’re working on a new transatomic-picometer-ply-giro-trimester-giga-mega​-implosion-submethod based on “rubber band” theory that would solve this issue.

9. domfonusr

Posts: 1084; Member since: Jan 17, 2014

Well, you know, "rubber band" theory actually eliminates the limitations of conventional electronics by storing potential energy in things like flywheels attached to various sizes of rubber bands, sometimes really big ones... when the packet hits a pocket on the socket, you have to measure whether the angle of the dangle is proportional to the heat of the beet... LOL!

10. Vokilam

Posts: 1191; Member since: Mar 15, 2018

That's exactly what I was saying.. ;)

11. shawman

Posts: 56; Member since: Sep 18, 2012

I dont think smaller process alone will bring greater performance improvements. it will help especially in power consumption as it will require lower voltage but Apple will make architectural changes to improve performance. But the improvements will start to taper off soon. Anyway their chips are already way too fast for a phone.

12. Well-Manicured-Man

Posts: 687; Member since: Jun 16, 2015

Not if these phones should run a full scale operating system at some point. And that is exactly what is going to happen.

13. geordie8t1

Posts: 298; Member since: Nov 16, 2015

Its all well and good but what's the point aside from bragging rights, you will still never fully utilize all that speed, I am perfectly happy with my S10+ even if it isn't the fastest on the market, most modern flagships are almost instant reaction times anyway, the apps are not good enough for the processing power inside the device

14. AmashAziz

Posts: 2921; Member since: Jun 30, 2014

There's something wrong with ur statement.

Latest Stories

This copy is for your personal, non-commercial use only. You can order presentation-ready copies for distribution to your colleagues, clients or customers at https://www.parsintl.com/phonearena or use the Reprints & Permissions tool that appears at the bottom of each web page. Visit https://www.parsintl.com/ for samples and additional information.