iPad Pro A9X chip breakdown shows 12 GPU cores and no L3 cache
Chipworks and AnandTech worked hard over the Thanksgiving break to get images of the A9X chip and sort out what is there and what isn't. The breakdown confirms that TSMC made the SoC using a 16nm FinFET process, and the full chip is roughly 147mm2 in die size, which makes it slightly larger than the A6X and A8X, but smaller than the A5X.
A large amount of that space is dedicated to fitting in 12 GPU cores as part of Imagination's PowerVR 12 cluster Series7 design, which doesn't even exist on Imagination's roadmap. The A9 chip used Imagination's 6-core PVR GT7600, but the A9X is in a strange grey area between the 8 core GT7800 and 16 core GT7900, so it doesn't get a fancy name. But, when you combine those 12 GPU cores with the 128-bit memory bus, the A9X is capable of pushing memory bandwidth of 51.2GB/sec, which is pretty impressive.
The A9X SoC also doesn't have an L3 cache, which is somewhat surprising. AnandTech posits that the omission of the L3 cache was acceptable because of the size of the memory bandwidth on the chip, or it may be that Apple simply didn't need the power-saving afforded by the L3 cache. The answer is likely a bit of both, but we'll never get confirmation from Apple, so it'll have to remain an educated guess.