Google joins Qualcomm on a quest for “low power, high performance” RISC-V chip for Wear OS
RISC-V chips are rarely mentioned, but this might change with Google’s latest collaboration with Qualcomm. Now, the two leading companies are joining forces to develop a “RISC-V Snapdragon Wear platform that will power next-generation Wear OS solutions”.
RISC-V (pronounced “risk-five”) is an open standard instruction set architecture and unlike most other ISA designs, RISC-V is provided under royalty-free open-source licenses. Basically, it’s an open-source alternative to ARM and x86 (via 9to5Google).
The Google-Qualcomm cooperation has been announced on Qualcomm’s official website and they highlight that this is how competition and innovation will thrive:
“This expanded framework will help pave the way for more products within the ecosystem to take advantage of custom CPUs that are low power and high performance. Leading up to this, the companies will continue to invest in Snapdragon Wear platforms as the leading smartwatch silicon provider for the Wear OS ecosystem”, leaders at Qualcomm point out.
Back in the Autumn of 2021, there were hints that Apple was heading in the RISC-V direction. The Cupertino company posted an open job position for someone with “Detailed knowledge of RISC-V”, but haven’t talked much about the open-source architecture since. They continue to rely on ARM’s architecture and they continue to pay royalties.
According to ARM, “RISC provides high performance per watt for battery operated devices where energy efficiency is key...for chip designers, RISC processors simplify the design and deployment process and provide a lower per-chip cost due to the smaller components required. Because of the reduced instruction set and simple decoding logic, less chip space is used, fewer transistors are required, and more general-purpose registers can fit into the central processing unit".
RISC-V (pronounced “risk-five”) is an open standard instruction set architecture and unlike most other ISA designs, RISC-V is provided under royalty-free open-source licenses. Basically, it’s an open-source alternative to ARM and x86 (via 9to5Google).
As an open-source instruction set architecture (ISA), RISC-V encourages innovation by allowing any company to develop completely custom cores. This allows more companies to enter the marketplace, which creates increased innovation and competition. RISC-V’s openness, flexibility, and scalability benefit the entire value chain – from silicon vendors to OEMs, end devices, and consumers.
They are actively working on the RISC-V wearable-based solution, but a date for the commercial product launch has not shared yet – the timing will be disclosed at a later date.
“This expanded framework will help pave the way for more products within the ecosystem to take advantage of custom CPUs that are low power and high performance. Leading up to this, the companies will continue to invest in Snapdragon Wear platforms as the leading smartwatch silicon provider for the Wear OS ecosystem”, leaders at Qualcomm point out.
Apple almost tried RISC-V
Back in the Autumn of 2021, there were hints that Apple was heading in the RISC-V direction. The Cupertino company posted an open job position for someone with “Detailed knowledge of RISC-V”, but haven’t talked much about the open-source architecture since. They continue to rely on ARM’s architecture and they continue to pay royalties.
According to ARM, “RISC provides high performance per watt for battery operated devices where energy efficiency is key...for chip designers, RISC processors simplify the design and deployment process and provide a lower per-chip cost due to the smaller components required. Because of the reduced instruction set and simple decoding logic, less chip space is used, fewer transistors are required, and more general-purpose registers can fit into the central processing unit".
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