Samsung announces its roadmap to chips made using 4nm process

Right now, top-of-the-line chipsets are being made using the 10nm process. Samsung has been among the leaders in hitting this target. The smaller the process size, the more powerful and energy efficient these chips become as more transistors can be placed on them. This relates to Moore's Law, devised by Intel co-founder Gordon Moore back in 1965. He noted that the number of transistors per square inch on integrated circuits doubled every two-years.

Samsung has produced a roadmap showing how it plans on going from the current 10nm process down to 4nm. According to a presentation made at the Samsung Foundry Forum, Samsung's next step is to produce 8nm chips using its Low Power Plus process. It's 7nm Lower Power Plus process will be the first to use Extreme Ultra Violet lithography, which is used to etch the circuit design onto a silicon wafer. By the time Samsung gets to its 6nm Low Power Plus process, it will use a new Smart Scaling solution that will allow for ultra-low power benefits.

From there, Samsung says that it will drop down to its 5nm Low Power Plus process, and then the target. The 4nm Low Power Plus process will be the first to use a next generation device architecture called Multi Bridge Channel FET. This is Samsung's Gate All Around FET technology that is designed to workaround the physical scaling and performance limitations of the FinFET architecture.

Getting from 10nm to 4nm is going to take time, and there will be obstacles and problems along the way. But as Samsung continues to check off each stop along the way to 4nm chips, consumers will get to enjoy faster performance from their mobile devices even while consuming less energy.

source: Samsung